CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

10.3.12 STOPMODE (0x2C) — STOP Mode

76543210

X X X X X X XX

This register exists only as an address decode and is used to enter STOP mode. It is very important that

DMA activity is stopped before this register is written to. The value written to the register is permanently

forced out on the main data bus during STOP mode, and for most systems it is desirable to ensure that

this value is 0xFFFFFFFF. The address bus is automatically forced high during STOP mode.

Write

(any value), enter STOP mode with OSCPOWER set low. The write to this

register completes on either wakeup event, nEVENT, nEVENT2, or reset

Read

ignored

10.3.13 FIQST (0x30) — FIQ Interrupts Status

76543210

1F0S00 I D

The FIQ control registers take a similar form to the IRQ registers previously described. Again, bit 7 is

always active so that a FIQ interrupt can be forced via software.

1

always active

F

nINT8, active-low

S

nINT6, active-low

I

INT5, active-high

D

INT9, active-high

Write

ignored

Read

status

0

1

inactive

active

10.3.14 FIQRQ (0x34) — FIQ Interrupts Request

76543210

1F0S00 I D

1

F

S

I

D

Write

Read

always active

nINT8, active-low

nINT6, active-low

INT5, active-high

INT9, active-high

ignored

request, status bitwise AND’ed with mask

June 1997

ADVANCE DATA BOOK v2.0

87

MEMORY AND I/O PROGRAMMERS’ MODEL

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