OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Timing Characteristics (continued)

Table 33A. OR2CxxA and OR2TxxA Sequential PFU Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Speed

Parameter

Symbol

-3

-4

-5

-6

-7

Unit

Min Max Min Max Min Max Min Max Min Max

S Input Requirements

Clock Low Time

TCL

2.5 — 2.0 — 1.8 — 1.7 — 1.6 — ns

Clock High Time

TCH

2.5 — 2.0 — 1.8 — 1.7 — 1.6 — ns

E Global S/R Pulse Width (GSRN)

TRW

2.5 — 2.0 — 1.8 — 1.7 — 1.6 — ns

Local S/R Pulse Width

TPW

2.5 — 2.0 — 1.8 — 1.7 — 1.6 — ns

Combinatorial Setup Times (TJ = 85 °C,

IC VDD = min):

D Four Input Variables to Clock

F4*_SET

1.7 — 1.3 — 1.1 — 1.0 — 0.9 — ns

(A[4:0], B[4:0] to CK)

Five Input Variables to Clock

F5*_SET

1.9 — 1.3 — 1.2 — 1.0 — 0.9 — ns

V (A[4:0], B[4:0] to CK)

E PFUMUX to Clock (A[4:0], B[4:0] to CK)

MUX_SET 2.9 — 2.3 — 2.1 — 1.6 — 1.5 — ns

PFUMUX to Clock (C0 to CK)

C0MUX_SET 1.2 — 0.9 — 0.8 — 0.7 — 0.6 — ns

PFUNAND to Clock (A[4:0], B[4:0] to CK)

ND_SET

2.9 — 2.2 — 2.0 — 1.7 — 1.6 — ns

E PFUNAND to Clock (C0 to CK)

C0ND_SET 1.2 — 0.6 — 0.5 — 0.5 — 0.5 — ns

U PFUXOR to Clock (A[4:0], B[4:0] to CK)

XOR_SET 3.6 — 3.0 — 2.7 — 2.1 — 2.0 — ns

PFUXOR to Clock (C0 to CK)

C0XOR_SET 1.2 — 0.9 — 0.8 — 0.7 — 0.6 — ns

Data In to Clock (WD[3:0] to CK)

D*_SET

0.1 — 0.1 — 0.0 — 0.1 — 0.1 — ns

D IN Clock Enable to Clock (CE to CK)

CKEN_SET 1.2 — 1.0 — 0.9 — 0.9 — 0.6 — ns

Local Set/Reset (synchronous) (LSR to CK)

LSR_SET 1.4 — 1.3 — 1.2 — 1.1 — 0.8 — ns

Data Select to Clock (SEL to CK)

SELECT_SET 1.5 — 1.4 — 1.3 — 1.2 — 1.0 — ns

Pad Direct In

PDIN_SET 0.0 — 0.0 — 0.0 — 0.0 — 0.0 — ns

T Combinatorial Hold Times (TJ = all, VDD = all):

T Data In (WD[3:0] from CK)

D*_HLD

0.4 — 0.4 — 0.4 — 0.3 — 0.3 — ns

Clock Enable (CE from CK)

CKEN_HLD 0.4 — 0.0 — 0.0 — 0.0 — 0.0 — ns

Local Set/Reset (synchronous) (LSR from CK) LSR_HLD 0.0 — 0.0 — 0.0 — 0.0 — 0.0 — ns

C N Data Select (sel from CK)

SELECT_HLD 0.0 — 0.0 — 0.0 — 0.0 — 0.0 — ns

Pad Direct In Hold (DIA[3:0], DIB[3:0] to CK)1 PDIN_HLD 1.4 — 1.0 — 0.9 — 0.8 — 0.8 — ns

All Others

—

0.0 — 0.0 — 0.0 — 0.0 — 0.0 — ns

E Output Characteristics

O Sequential Delays (TJ = 85 °C, VDD = min):

Local S/R (async) to PFU Out (LSR to Q[3:0])

L Global S/R to PFU Out (GSRN to Q[3:0])

E C Clock to PFU Out (CK to Q[3:0])—Register

Clock to PFU Out (CK to Q[3:0])—Latch

Transparent Latch (WD[3:0] to Q[3:0])

LSR_DEL

GSR_DEL

REG_DEL

LTCH_DEL

LTCH_DDEL

— 3.4 — 3.1 — 2.5 — 2.0 — 1.6 ns

— 2.3 — 2.0 — 1.6 — 1.3 — 1.2 ns

— 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns

— 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns

— 2.7 — 2.5 — 2.0 — 2.0 — 1.8 ns

S DIS 1.The input buffers contain a programmable delay to allow the hold time vs. the external clock pin to be equal to 0.

136

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