ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

9.4 Programmer Model

9.4.1

Processor Operating Modes

The following operation modes are present in all states:

 User mode (USR) is the usual ARM program execution state. It is used for executing most application

programs.

 Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or

channel process.

 Interrupt (IRQ) mode is used for general-purpose interrupt handling.

 Supervisor mode (SVC) is a protected mode for the operating system.

 Abort mode (ABT) is entered after a data or instruction prefetch abort.

 System mode (SYS) is a privileged user mode for the operating system.

 Undefined mode (UND) is entered when an undefined instruction exception occurs.

Mode changes may be made under software control, or may be brought about by external interrupts or exception

processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes,

are entered in order to service interrupts or exceptions or to access protected resources.

9.4.2

Processor Operating States

The processor has the following instruction set states controlled by the T bit and J bit in the CPSR.

 ARM state:

The processor executes 32-bit, word-aligned ARM instructions.

 Thumb state:

The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions.

 ThumbEE state:

The processor executes a variant of the Thumb instruction set designed as a target for dynamically

generated code. This is code compiled on the device either shortly before or during execution from a

portable bytecode or other intermediate or native representation.

 Jazelle state:

The processor executes variable length, byte-aligned Java bytecodes.

The J bit and the T bit determine the instruction set used by the processor. Table 9-1 shows the encoding of these

bits.

Table 9-1. CPSR J and T Bit Encoding

J

T

Instruction Set State

0

0

ARM

0

1

Thumb

1

0

Jazelle

1

1

ThumbEE

Changing between ARM and Thumb states does not affect the processor mode or the register contents. See the

ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for information on entering and exiting

ThumbEE state.

42 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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