ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

9.5.3

TLB Organization

TLB Organization is described in the sections that follow:

 Micro TLB

 Main TLB

9.5.3.1 Micro TLB

The first level of caching for the page table information is a micro TLB of 10 entries that is implemented on each of

the instruction and data sides. These blocks provide a lookup of the virtual addresses in a single cycle.

The micro TLB returns the physical address to the cache for the address comparison, and also checks the access

permissions to signal either a Prefetch Abort or a Data Abort.

All main TLB related maintenance operations affect both the instruction and data micro TLBs, causing them to be

flushed. In the same way, any change of the following registers causes the micro TLBs to be flushed:

 Context ID Register (CONTEXTIDR)

 Domain Access Control Register (DACR)

 Primary Region Remap Register (PRRR)

 Normal Memory Remap Register (NMRR)

 Translation Table Base Registers (TTBR0 and TTBR1)

9.5.3.2 Main TLB

Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the main TLB

take a variable number of cycles, according to competing requests from each of the micro TLBs and other

implementation-dependent factors.

The main TLB is 128-entry two-way set-associative.

TLB match process

Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each

is marked as being associated with a particular application space (ASID), or as global for all application spaces.

The CONTEXTIDR determines the currently selected application space.

A TLB entry matches when these conditions are true:

 Its virtual address matches that of the requested address.

 Its Non-secure TLB ID (NSTID) matches the Secure or Non-secure state of the MMU request.

 Its ASID matches the current ASID in the CONTEXTIDR or is global.

The operating system must ensure that, at most, one TLB entry matches at any time. The TLB can store entries

based on the following block sizes:

Supersections

Sections

Large pages

Small pages

Describe 16 Mbyte blocks of memory

Describe 1 Mbyte blocks of memory

Describe 64 Kbyte blocks of memory

Describe 4 Kbyte blocks of memory

Supersections, sections and large pages are supported to permit mapping of a large region of memory while using

only a single entry in the TLB. If no mapping for an address is found within the TLB, then the translation table is

automatically read by hardware and a mapping is placed in the TLB.

SAMA5D3 Series [DATASHEET]

49

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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