ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATSAMA5D35A-CU Datasheet PDF : 1917 Pages
| |||
9.5.2
Memory Management System
The Cortex-A5 processor supports the ARM v7 VMSA . The translation of a Virtual Address (VA) used by the
instruction set architecture to a Physical Address (PA) used in the memory system and the management of the
associated attributes and permissions is carried out using a two-level MMU.
The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches
(IuTLB) and in the DPU for data read and write requests (DuTLB).
A miss in the micro TLB results in a request to the main unified TLB shared between the data and instruction sides
of the memory system. The TLB consists of a 128-entry two-way set-associative RAM based structure. The TLB
page-walk mechanism supports page descriptors held in the L1 data cache. The caching of page descriptors is
configured globally for each translation table base register, TTBRx, in the system coprocessor, CP15.
The TLB contains a hitmap cache of the page types which have already been stored in the TLB.
9.5.2.1 Memory types
Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not
implement all possible combinations:
Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable.
The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same
way as inner shareable.
Write-back no write-allocate is not supported. It is treated as write-back write-allocate.
Table 9-5 shows the treatment of each different memory type in the Cortex-A5 processor in addition to the
architectural requirements.
Table 9-5. Treatment of Memory Attributes
Memory Type Attribute Shareability Other Attributes
Strongly Ordered
—
—
Device
Non-shareable —
Shareable —
Non-cacheable
Write-through cacheable
Non-shareable Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Non-cacheable
Normal
Inner
shareable
Write-through cacheable
Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Non-cacheable
Outer
shareable
Write-through cacheable
Write-back cacheable,
write allocate
Write-back cacheable,
no write allocate
Notes
—
—
—
Does not access L1 caches
Treated as non-cacheable
Can dynamically switch to no write allocate, if more than
three full cache lines are written in succession
Treated as non-shareable write-back cacheable, write
allocate
—
Treated as inner shareable non-cacheable
Treated as inner shareable non-cacheable unless the SMP
bit in the Auxiliary Control Register is set (ACTLR[6] = b1).
If this bit is set the area is treated as write-back cacheable
write allocate.
Treated as inner shareable non-cacheable
Treated as inner shareable non-cacheable unless the SMP
bit in the Auxiliary Control Register is set (ACTLR[6] = b1).
If this bit is set the area is treated as write-back cacheable
write allocate.
48 SAMA5D3 Series [DATASHEET]
Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16
Share Link: 