ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:

 hold information about the most recently performed ALU operation

 control the enabling and disabling of interrupts

 set the processor operation mode

Figure 9-2.

Status Register Format

31 30 29 28 27

24 23

20 19

16 15

N

Z

C

V

Q

IT

[1:0]

J

Reserved

GE[3:0]

10 9 8 7 6 5 4

0

IT[7:2] E A I F T Mode

 N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags

 Q: cumulative saturation flag

 IT: If-Then execution state bits for the Thumb IT (If-Then) instruction

 J: Jazelle bit, see the description of the T bit

 GE: Greater than or Equal flags, for SIMD instructions

 E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is

ignored by instruction fetches.

̶ E = 0: Little endian operation

̶ E = 1: Big endian operation

 A: Asynchronous abort disable bit. Used to mask asynchronous aborts.

 I: Interrupt disable bit. Used to mask IRQ interrupts.

 F: Fast interrupt disable bit. Used to mask FIQ interrupts.

 T: Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state

of the processor, ARM, Thumb, Jazelle, or ThumbEE.

 Mode: five bits to encode the current processor mode. The effect of setting M[4:0] to a reserved value is

UNPREDICTABLE.

Table 9-3.

Processor Mode vs. Mode Field

Mode

USR

FIQ

IRQ

SVC

ABT

UND

SYS

Reserved

M[4:0]

10000

10001

10010

10011

10111

11011

11111

Other

44 SAMA5D3 Series [DATASHEET]

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

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