ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation
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ATSAMA5D35A-CU Datasheet PDF : 1917 Pages
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9.4.2.1 Switching State
It is possible to change the instruction set state of the processor between:
ARM state and Thumb state using the BX and BLX instructions.
Thumb state and ThumbEE state using the ENTERX and LEAVEX instructions.
ARM and Jazelle state using the BXJ instruction.
Thumb and Jazelle state using the BXJ instruction.
See the ARM Architecture Reference Manual for more information about changing instruction set state.
9.4.3
Cortex-A5 Registers
This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and
Program Counter (PC). These registers are selected from a total set of either 31 or 33 registers, depending on
whether or not the Security Extensions are implemented. The current execution mode determines the selected set
of registers, as shown in Table 9-2. This shows that the arrangement of the registers provides duplicate copies of
some registers, with the current register selected by the execution mode. This arrangement is described as
banking of the registers, and the duplicated copies of registers are referred to as banked registers.
Table 9-2. Cortex-A5 Modes and Registers Layout
User and
System
Monitor
Supervisor
R0
R0
R0
R1
R1
R1
R2
R2
R2
R3
R3
R3
R4
R4
R4
R5
R5
R5
R6
R6
R6
R7
R7
R7
R8
R8
R8
R9
R9
R9
R10
R10
R10
R11
R11
R11
R12
R12
R12
R13
R13_MON
R13_SVC
R14
R14_MON
R14_SVC
PC
PC
PC
Abort
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_ABT
R14_ABT
PC
Undefined
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_UND
R14_UND
PC
Interrupt
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_IRQ
R14_IRQ
PC
Fast Interrupt
R0
R1
R2
R3
R4
R5
R6
R7
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
CPSR
SPSR_MON
CPSR
SPSR_SVC
CPSR
SPSR_ABT
CPSR
SPSR_UND
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ
Mode-specific banked registers
SAMA5D3 Series [DATASHEET]
43
Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16
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