ATSAMA5D35A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATSAMA5D35A-CU

SMART ARM-based MPU

Atmel Corporation 

9.4.5

Addresses in the Cortex-A5 processor

The Cortex-A5 processor operates using virtual addresses (VAs). The Memory Management Unit (MMU)

translates these VAs into the physical addresses (PAs) used to access the memory system. Translation tables

hold the mappings between VAs and PAs.

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for more information.

When the Cortex-A5 processor is executing in Non-secure state, the processor performs translation table look-ups

using the Non-secure versions of the Translation Table Base Registers. In this situation, any VA can only translate

into a Non-secure PA. When it is in Secure state, the Cortex-A5 processor performs translation table look-ups

using the Secure versions of the Translation Table Base Registers. In this situation, the security state of any VA is

determined by the NS bit of the translation table descriptors for that address.

Following is an example of the address manipulation that occurs when the Cortex-A5 processor requests an

instruction:

1. The Cortex-A5 processor issues the VA of the instruction as Secure or Non-secure VA accesses according

to the state the processor is in.

2. The instruction cache is indexed by the bits of the VA. The MMU performs the translation table look-up in

parallel with the cache access. If the processor is in the Secure state it uses the Secure translation tables,

otherwise it uses the Non-secure translation tables.

3. If the protection check carried out by the MMU on the VA does not abort and the PA tag is in the instruction

cache, the instruction data is returned to the processor.

4. If there is a cache miss, the MMU passes the PA to the AXI bus interface to perform an external access. The

external access is always Non-secure when the core is in the Non-secure state. In the Secure state, the

external access is Secure or Non-secure according to the NS attribute value in the selected translation table

entry. In Secure state, both L1 and L2 translation table walk accesses are marked as Secure, even if the first

level descriptor is marked as NS.

9.5 Memory Management Unit

9.5.1

About the MMU

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also

controls accesses to and from external memory.

The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:

 Page table entries that support:

̶ 16 Mbyte supersections. The processor supports supersections that consist of 16 Mbyte blocks of

memory.

̶ 1 Mbyte sections

̶ 64 Kbyte large pages

̶ 4 Kbyte small pages

 16 access domains

 Global and application-specific identifiers to remove the requirement for context switch TLB flushes.

 Extended permissions checking capability.

TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated

with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system.

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for a full architectural description of

the ARMv7 VMSA.

SAMA5D3 Series [DATASHEET]

47

Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16

Share Link: