9.4.3.1 CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list
below:
Cortex A5
Caches (ICache, DCache and write buffer)
MMU
Security
Other system options
To control these features, CP15 provides 16 additional registers. See Table 9-4.
Table 9-4. CP15 Registers
Register
Name
Read/Write
0
ID Code(1)
Read/Unpredictable
0
Cache type(1)
Read/Unpredictable
1
Control(1)
Read/Write
1
Security(1)
Read/Write
2
Translation Table Base
Read/Write
3
Domain Access Control
Read/Write
4
Reserved
None
5
Data fault Status(1)
Read/Write
5
Instruction fault status
Read/Write
6
Fault Address
Read/Write
7
Cache and MMU Operations(1)
Read/Write
8
TLB operations
Unpredictable/Write
9
Cache lockdown(1)
Read/Write
10
TLB lockdown
Read/Write
11
Reserved
None
12
Interrupts management
Read/Write
13
FCSE PID(1)
13
Context ID(1)
Read/Write
Read/Write
14
Reserved
None
15
Test configuration
Read/Write
Note: 1. This register provides access to more than one register. The register accessed depends on the value of the CRm
field or Opcode_2 field.
SAMA5D3 Series [DATASHEET]
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Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16