ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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ADP3193A
POWER MOSFETS
For our example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3120A) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are recommended.
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3193A, currents are balanced between phases; therefore,
the current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, Equation 19 shows the total power that is
dissipated in each synchronous MOSFET in terms of the ripple
current per phase (IR) and the average total output current (IO):
PSF
=
(1
−
D
)
×
⎢⎢⎣⎡⎜⎜⎝⎛
IO
nSF
⎟⎟⎠⎞ 2
+
1
12
×
⎜⎜⎝⎛
n IR
nSF
⎟⎟⎠⎞
2
⎤
⎥
⎥⎦
×
R DS ( SF
)
(19)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, the user can find the
required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Therefore, for this example
(56 A maximum), RDS(SF) (per MOSFET) is less than 4.7 mΩ. This
RDS(SF) is also at a junction temperature of about 120°C. As a result,
users need to account for this when making this selection. This
example uses two low-side MOSFETs at 4.8 mΩ, each at 120°C.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to the input must be small (less than 10% is recom-
mended) to prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.
In addition, the time to switch the synchronous MOSFETs off
should not exceed the nonoverlap dead time of the MOSFET
driver (45 ns typical for the ADP3120A). The output impedance
of the driver is approximately 2 Ω, and the typical MOSFET
input gate resistances are about 1 Ω to 2 Ω. Therefore, a total
gate capacitance of less than 6000 pF should be adhered to.
Because two MOSFETs are in parallel, the input capacitance for
each synchronous MOSFET should be limited to 6000 pF.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
PS( MF )
=2×
f SW
× VCC × IO
n MF
× RG
× nMF
n
× C ISS
(20)
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance (2 Ω for the ADP3120A and about
1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω).
CISS is the input capacitance of the main MOSFET.
Adding more main MOSFETs (nMF) does not help the switching
loss per MOSFET because the additional gate capacitance slows
switching. Use lower gate capacitance devices to reduce
switching loss.
The conduction loss of the main MOSFET is given by the
following:
PC(MF )
=
D
×
⎢⎢⎣⎡⎜⎜⎝⎛
IO
nMF
⎟⎟⎠⎞2
+
1
12
×
⎜⎜⎝⎛
n× IR
nMF
⎟⎟⎠⎞2
⎤
⎥
⎥⎦
× RDS(MF )
(21)
where RDS(MF) is the on resistance of the MOSFET.
Typically, for main MOSFETs, the highest speed (low CISS)
device is preferred, but such devices usually have higher on
resistance. Select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the switching
and conduction losses.
For this example, an NTD40N03L is selected as the main MOSFET
(three total, nMF = 3), with CISS = 584 pF (maximum) and RDS(MF) =
19 mΩ (maximum at TJ = 120°C). An NTD110N02L is selected as
the synchronous MOSFET (three total, nSF = 3), with CISS = 2710 pF
(maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The
synchronous MOSFET CISS is less than 6000 pF, satisfying this
requirement.
Solving for the power dissipation per MOSFET at IO = 56 A and
IR = 11.7 A yields 1.53 W for each synchronous MOSFET and
1.06 W for each main MOSFET. As a guide, limit the MOSFET
power dissipation to 1.5 W. The values calculated in Equation 20
and Equation 21 will comply with this guideline.
Finally, consider the power dissipation in the driver for each
phase. This is best expressed as QG for the MOSFETs and is
given by Equation 22.
( ) PDRV
=
⎡
⎢
⎢⎣
f
2
SW
×n
×
nMF × QGMF + nSF × QGSF
⎤
+
I CC
⎥
⎥⎦
× VCC
(22)
where QGMF is the total gate charge for each main MOSFET, and
QGSF is the total gate charge for each synchronous MOSFET
Also shown is the standby dissipation factor (ICC × VCC) of the
driver. For the ADP3120A, the maximum dissipation should be
Rev. 0 | Page 23 of 32
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