ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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VTRAN1 by the amount of ripple while still meeting the
specifications.
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing capaci-
tors, also check the output ripple voltage to ensure that it is still
within specifications.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
For good results, a PCB with at least four layers is recommended.
This provides the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power-delivery current paths.
Keep in mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
When high currents must be routed between PCB layers, use
vias liberally to create several parallel current paths so that the
resistance and inductance introduced by these current paths are
minimized and the via current rating is not exceeded.
If critical signal lines (including the output voltage sense lines of
the ADP3193A) must cross through power circuitry, it is best to
interpose a signal ground plane between those signal lines and
the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
increasing signal ground noise.
An analog ground plane should be used around and under the
ADP3193A as a reference for the components associated with
the controller. This plane should be tied to the nearest output-
decoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing into it.
The components around the ADP3193A should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are those to the FB and
CSSUM pins. The output capacitors should be connected as
close as possible to the load (or connector) that receives the
power, for example, as close as possible to a microprocessor
core. If the load is distributed, the capacitors should also be
distributed and placed in greater proportion where the load
tends to be more dynamic.
Avoid crossing any signal lines over the switching power path loop
(described in the Power Circuitry Recommendations section).
ADP3193A
Power Circuitry Recommendations
The switching power path on the PCB should be routed to
encompass the shortest possible length to minimize radiated
switching noise energy (that is, EMI) and conduction losses in
the board. Failure to take proper precautions often results in
EMI problems for the entire PC system and noise-related
operational problems in the power-converter control circuitry.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs,
including all interconnecting PCB traces and planes. Using
short, wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the switching
loop, which can cause high energy ringing, and it accommodates
the high current demand with minimal voltage loss.
When a power-dissipating component, such as a power MOSFET,
is soldered to a PCB, it is recommended to use vias liberally both
directly on the mounting pad and immediately surrounding it. Two
important reasons for this are improved current rating through
the vias and improved thermal performance from vias extended
to the opposite side of the PCB, where a plane can more readily
transfer the heat to the air. Make a mirror image on the opposite
side of the PCB of any pad being used to heat-sink the MOSFETs.
This helps achieve the best thermal dissipation in the air around
the board. To further improve thermal performance, use the largest
pad area possible.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers, extending fully under all the
power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB and
FBRTN pins, which connect to the signal ground at the load. To
avoid differential mode noise pickup in the sensed signal, the
loop area should be small. Therefore, the FB and FBRTN traces
should be routed adjacent to each other on top of the power
ground plane back to the controller.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor, and the CSREF signal
should be connected to the output voltage at the nearest
inductor to the controller.
Rev. 0 | Page 29 of 32
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