ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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ADP3193A
The compensation values can then be solved using
CA
=
n × RO × TA
RE × RB
=
3×1 mΩ × 2.47 μs
45.3mΩ ×1.27 kΩ
= 128 pF
(35)
RA
=
TC
CA
=
3.53 μs
128 pF
= 27.5 kΩ
(36)
CB
=
TB
RB
=
1120 ns
1.27 kΩ
= 882 pF
(37)
C FB
=
TD
RA
=
466 ns
27.5 kΩ
= 16.9 pF
(38)
These equations result in the starting values prior to tuning the
design that account for layout and other parasitic effects (see
the Tuning Procedure for ADP3193A section). The final values
selected after tuning are
CA = 220 pF
RA = 22.1 kΩ
CBB = 560 pF
CFB = 15 pF
Figure 12 and Figure 13 show the typical transient response
using these compensation values.
20mV/DIV
2µs/DIV
Figure 12. Typical Transient Response for Design Example Load Step
20mV/DIV
2µs/DIV
Figure 13. Typical Transient Response for Design Example Load Release
CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth the
maximum output current. To prevent large voltage transients,
use a low ESR input capacitor sized for the maximum rms
current. The maximum rms capacitor current is given by
I CRMS = D × I O ×
1 −1
N×D
(39)
ICRMS = 0.117 × 65A ×
1 − 1 = 10.3A
3 × 0.117
The capacitor manufacturer’s ripple-current ratings are often
based on only 2000 hours of life. As a result, it is advisable to
further derate the capacitor or to choose a capacitor rated at a
higher temperature than is required. Several capacitors can be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2700 μF, 16 V aluminum electrolytic capacitors and eight
4.7 μF ceramic capacitors.
To reduce the input current, di/dt, to a level below the recom-
mended maximum of 0.1 A/μs, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.
SHUNT RESISTOR DESIGN
The ADP3193A uses a shunt to generate 5 V from the 12 V
supply range. A trade-off can be made between the power
dissipated in the shunt resistor and the UVLO threshold.
Figure 14 shows the typical resistor value needed to realize
certain UVLO voltages and the maximum power dissipated in
the shunt resistor for these UVLO voltages.
550
0.50
500
0.45
450
PSHUNT
400
RSHUNT
0.40
0.35
350
0.30
300
0.25
250
0.20
200
0.15
150
0.10
7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0
VIN (UVLO)
Figure 14. Typical Shunt Resistor Value and Power Dissipation
for Different UVLO Voltages
Rev. 0 | Page 26 of 32
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