ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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ADP3193A
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3193A allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is entirely resistive over the widest possible frequency range,
including dc, and that is equal to the droop resistance (RO). With
the resistive output impedance, the output voltage droops in
proportion to the load current at any load current slew rate.
This ensures optimal positioning and minimizes the output
decoupling.
Because of the multimode feedback structure of the ADP3193A, it
is necessary to set the feedback compensation so that the converter
output impedance works in parallel with the output decoupling
to make the load look entirely resistive. In addition, it is necessary
to compensate for several poles and zeros created by the output
inductor and the decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is adequate for
proper compensation of the output filter.
Equation 30 to Equation 34 are intended to yield an optimal
starting point for the design; some adjustments may be necessary
to account for PCB and component parasitic effects (see the
Tuning Procedure for ADP3193A section).
First, compute the time constants for all the poles and zeros in
the system using Equation 30 to Equation 34.
( ) RE
= n × RO
+
AD
×
R DS
+
RL × VRT
VVID
+ 2× L × 1− n × D × VRT
n × C X × RO × VVID
1.4 mΩ × 0.79 V 2 × 320 nH × (1− 0.35) × 0.79 V
RE = 3 × 1 mΩ + 5 × 4.8 mΩ +
1.4 V
+
= 45.3 mΩ
3 × 4.48 mF × 1 mΩ × 1.4 V
( ) ( ) TA
= CX
×
RO
− R'
+
LX
RO
×
RO − R'
RX
= 4.48 mF ×
1 mΩ − 0.5 mΩ
+
347 pH
1 mΩ
1 mΩ − 0.5 mΩ
×
0.75 mΩ
= 2.47 μs
( ) ( ) TB = RX + R' − RO × C X = 0.75 mΩ + 0.5 mΩ − 1 mΩ × 4.48 mF = 1120 ns
(30)
(31)
(32)
TC
=
VRT
×
⎜⎛
⎜⎝
L
−
VVID
AD × RDS
2 × f SW
× RE
⎟⎞
⎟⎠
=
0.79
V
×
⎜⎛
⎜⎝
320
nH
−
5 × 4.8
2 × 330
mΩ
kHz
1.4 V × 45.3 mΩ
⎟⎞
⎟⎠
=
3.53 μs
(33)
( )( ) TD
=
CX
C X × C Z × RO2
× (RO − R')+ CZ
× RO
=
4.48 mF × 260 μF × 1 mΩ 2
4.48 mF × 1 mΩ − 0.5 mΩ + 260 μF × 1 mΩ
= 466 ns
(34)
where:
R' is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.5 mΩ (assuming a 4-layer, 1 oz motherboard).
RDS is the total low-side MOSFET on resistance per phase.
AD = 5.
VRT = 0.79 V.
LX = 347 pH for the eight aluminum-poly capacitors.
Rev. 0 | Page 25 of 32
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