DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

5.0 FLASH PROGRAM MEMORY

Note 1: This data sheet summarizes the

features of the dsPIC33EVXXXGM00X/

10X family of devices. It is not intended

to be a comprehensive reference

source. To complement the information

in this data sheet, refer to “Flash Pro-

gramming” (DS70609) in the “dsPIC33/

PIC24 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The dsPIC33EVXXXGM00X/10X family devices

contain internal Flash program memory for storing and

executing application code. The memory is readable,

writable and erasable during normal operation over the

entire VDD range.

The Flash memory can be programmed in the following

three ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self-Programming (RTSP)

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

ICSP allows for a dsPIC33EVXXXGM00X/10X family

device to be serially programmed while in the end

application circuit. This is done with two lines for

programming clock and programming data (PGECx/

PGEDx) lines, and three other lines for power (VDD),

ground (VSS) and Master Clear (MCLR). This allows

customers to manufacture boards with unprogrammed

devices and then program the device just before

shipping the product. This also allows the most recent

firmware or a custom firmware to be programmed.

Enhanced ICSP uses an on-board bootloader, known as

the Program Executive (PE), to manage the programming

process. Using an SPI data frame format, the Program

Executive can erase, program and verify program

memory. For more information on Enhanced ICSP, refer

to the specific device programming specification.

RTSP is accomplished using the TBLRD (Table Read)

and TBLWT (Table Write) instructions. With RTSP, the

user application can write program memory data as a

double program memory word, a row of 64 instructions

(192 bytes) and erase program memory in blocks of

512 instruction words (1536 bytes) at a time.

5.1 Table Instructions and Flash

Programming

The Flash memory read and the double-word

programming operations make use of the TBLRD and

TBLWT instructions, respectively. These allow direct read

and write access to the program memory space from the

data memory while the device is in normal operating

mode. The 24-bit target address in the program memory

is formed using bits<7:0> of the TBLPAG register and

the Effective Address (EA) from a W register, specified

in the table instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of the program memory.

TBLRDL and TBLWTL can access program memory in

both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read

or write to bits<23:16> of the program memory.

TBLRDH and TBLWTH can also access program

memory in Word or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Using

Program Counter

0

Program Counter

0

Using

Table Instruction

1/0 TBLPAG Reg

8 Bits

Working Reg EA

16 Bits

User/Configuration

Space Select

24-Bit EA

 2013-2016 Microchip Technology Inc.

Byte

Select

DS70005144E-page 83

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