DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)

bit 3-0

NVMOP<3:0>: NVM Operation Select bits(1,3,4)

1111 = Reserved

1110 = User memory and executive memory bulk erase operation

1101 = Reserved

1100 = Reserved

1011 = Reserved

1010 = Reserved

1001 = Reserved

1000 = Reserved

0111 = Reserved

0101 = Reserved

0100 = Reserved

0011 = Memory page erase operation

0010 = Memory row program operation

0001 = Memory double-word(5)

0000 = Reserved

Note 1:

2:

3:

4:

5:

These bits can only be reset on a POR.

If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.

All other combinations of NVMOP<3:0> are unimplemented.

Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.

Two adjacent words on a 4-word boundary are programmed during execution of this operation.

 2013-2016 Microchip Technology Inc.

DS70005144E-page 87

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