DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

5.4 Error Correcting Code (ECC)

In order to improve program memory performance and

durability, these devices include Error Correcting Code

functionality (ECC) as an integral part of the Flash

memory controller. ECC can determine the presence of

single-bit errors in program data, including which bit is

in error, and correct the data automatically without user

intervention. ECC cannot be disabled.

When data is written to program memory, ECC

generates a 7-bit Hamming code parity value for every

two (24-bit) instruction words. The data is stored in

blocks of 48 data bits and 7 parity bits; parity data is not

memory-mapped and is inaccessible. When the data is

read back, the ECC calculates the parity on it and

compares it to the previously stored parity value. If a

parity mismatch occurs, there are two possible

outcomes:

• Single-bit errors are automatically identified and

corrected on read-back. An optional device-level

interrupt (ECCSBEIF) is also generated.

• Double-bit errors will generate a generic hard trap

and the read data is not changed. If special

exception handling for the trap is not

implemented, a device Reset will also occur.

To use the single-bit error interrupt, set the ECC

Single-Bit Error Interrupt Enable bit (ECCSBEIE) and

configure the ECCSBEIP bits to set the appropriate

interrupt priority.

Except for the single-bit error interrupt, error events are

not captured or counted by hardware. This functionality

can be implemented in the software application, but it

is the user’s responsibility to do so.

5.5 Flash Memory Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

5.5.1 KEY RESOURCES

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

5.6 Control Registers

The following five SFRs are used to read and write the

program Flash memory: NVMCON, NVMKEY,

NVMADR, NVMADRU and NVMSRCADR.

The NVMCON register (Register 5-1) selects the

operation to be performed (page erase, word/row

program, inactive panel erase) and initiates the

program/erase cycle.

NVMKEY (Register 5-4) is a write-only register that is

used for write protection. To start a programming or

erase sequence, the user application must

consecutively write 0x55 and 0xAA to the NVMKEY

register.

There are two NVM Address registers: NVMADRU and

NVMADR. These two registers, when concatenated,

form the 24-bit Effective Address (EA) of the selected

word/row for programming operations or the selected

page for erase operations. The NVMADRU register is

used to hold the upper 8 bits of the EA, while the

NVMADR register is used to hold the lower 16 bits of

the EA. For row programming operation, data to be

written to program Flash memory is written into data

memory space (RAM) at an address defined by the

NVMSRCADR register (location of the first element in

row programming data).

 2013-2016 Microchip Technology Inc.

DS70005144E-page 85

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