DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33EV64GM102-I/SO

16-Bit, 5V Digital Signal Controllers with PWM, SENT, Op Amps and Advanced Analog Features

Microchip Technology 

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER

R/SO-0

R/W-0

R/W-0

R/W-0

U-0

WR(1)

WREN(1) WRERR(1) NVMSIDL(2)

—

bit 15

U-0

R/W-0

—

RPDF

R/W-0

URERR

bit 8

U-0

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

—

—

NVMOP3(1,3,4) NVMOP2(1,3,4) NVMOP1(1,3,4) NVMOP0(1,3,4)

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

SO = Settable Only bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11-10

bit 9

bit 8

bit 7-4

WR: Write Control bit(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is

cleared by hardware once the operation is complete

0 = Program or erase operation is complete and inactive

WREN: Write Enable bit(1)

1 = Flash program or erase operations are enabled

0 = Flash program or erase operations are inhibited

WRERR: Write Sequence Error Flag bit(1)

1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0 = The program or erase operation completed normally

NVMSIDL: NVM Stop in Idle Control bit(2)

1 = Primary Flash operation discontinues when the device enters Idle mode

0 = Primary Flash operation continues when the device enters Idle mode.

Unimplemented: Read as ‘0’

RPDF: Row Programming Data Format Control bit

1 = Row data to be stored in RAM is in a compressed format

0 = Row data to be stored in RAM is in an uncompressed format

URERR: Row Programming Data Underrun Error Flag bit

1 = Row programming operation has been terminated due to a data underrun error

0 = No data underrun has occurred

Unimplemented: Read as ‘0’

Note 1:

2:

3:

4:

5:

These bits can only be reset on a POR.

If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.

All other combinations of NVMOP<3:0> are unimplemented.

Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.

Two adjacent words on a 4-word boundary are programmed during execution of this operation.

DS70005144E-page 86

 2013-2016 Microchip Technology Inc.

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