T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 8. T2080 I/O power dissipation (continued)
I/O Power supply
Parameter
Typical (mW)
Maximum (mW)
Notes
SerDes, 1.35 V XVDD
2x 3 G-baud
70
80
SerDes, 1.35 V XVDD SRIO
1x 2.5 G-baud
50
60
SerDes, 1.35 V XVDD
2x 2.5 G-baud
80
90
SerDes, 1.35 V XVDD
4x 2.5 G-baud
140
150
SerDes, 1.35 V XVDD
1x 3.125 G-baud 50
60
SerDes, 1.35 V XVDD
2x 3.125 G-baud 80
90
SerDes, 1.35 V XVDD
4x 3.125 G-baud 140
150
SerDes, 1.35 V XVDD
1x 5 G-baud
50
70
SerDes, 1.35 V XVDD
2x 5 G-baud
90
100
SerDes, 1.35 V XVDD
4x 5 G-baud
150
160
SerDes, 1.35 V XVDD PEX2.0
1x 5 G-baud
50
70
SerDes, 1.35 V XVDD
2x 5 G-baud
90
100
SerDes, 1.35 V XVDD
4x 5 G-baud
150
160
SerDes, 1.35 V XVDD
8x 5 G-baud
280
290
SerDes, 1.35 V XVDD PEX3.0
1x 8 G-baud
60
70
SerDes, 1.35 V XVDD
2x 8 G-baud
100
110
SerDes, 1.35 V XVDD
4x 8 G-baud
170
190
SerDes, 1.35 V XVDD XFI
1x 10 G-baud
60
70
SerDes, 1.35 V XVDD
2x 10 G-baud
100
110
SerDes, 1.35 V XVDD
4x 10 G-baud
170
190
Fuse
PROG_SFG
—
—
173
1, 8
Programming
Override
Thermal Monitor TH_VDD
—
—
18
1
Unit
Notes:
1. The maximum values are dependent on actual use case such as what application, external components used,
environmental conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed
power. Expect different results depending on the use case. The maximum values are estimated and they are based on
simulations at 105 °C junction temperature.
2. Typical DDR power numbers are based on one 2-rank DIMM with 40% utilization.
3. Assuming 15 pF total capacitance load.
4. GPIOs are supported on 1.8 V and 2.5 V rails as specified in the hardware specification.
5. Maximum DDR power numbers are based on one 2-rank DIMM with 100% utilization.
6. The typical values are estimates and based on simulations at nominal recommended voltage for the I/O power supply and
assuming at 65° C junction temperature.
7. The total power numbers of XVDD is dependent on customer application use case. This table lists all the SerDes
configurations possible for the device. To get the XVDD power numbers, the user should add the combined lanes to match to
the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes.
8. The max power requirement is during programming. No active power beyond leakage levels should be drawn and the
supply must be grounded when not programming.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
55
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