T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

3.5 Power-on ramp rate

Electrical characteristics

This section describes the AC electrical specifications for the power-on ramp rate

requirements. Controlling the maximum power-on ramp rate is required to avoid excess

in-rush current.

This table provides the power supply ramp rate specifications.

Table 11. Power supply ramp rate

Parameter

Min

Max

Unit Notes

Required ramp rate for all voltage supplies (including OVDD/DVDD/ G1VDD/

—

25

V/ms

1, 2

SnVDD/XnVDD/LVDD, all core and platform VDD supplies, D1_MVREF, all AVDD, and

CVDD supplies.)

Required ramp rate for PROG_SFP

—

25

V/ms

1, 2

Notes:

1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of

change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.

2. Over full recommended operating temperature range (see Table 3).

3.6 Input clocks

3.6.1 System clock (SYSCLK) timing specifications

This section provides the system clock DC and AC timing specifications.

3.6.1.1 System clock DC timing specifications

This table provides the system clock (SYSCLK) DC specifications.

Table 12. SYSCLK DC electrical characteristics3

Parameter

Symbol

Min

Typical

Max

Unit

Input high voltage

VIH

Input low voltage

VIL

Input capacitance

CIN

Input current (OVIN= 0 V or OVIN =

IIN

OVDD)

Note:

1.25

—

—

—

—

7

-50

—

—

V

0.6

V

12

pF

+50

μA

1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.

2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.

3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.

Notes

1

1

—

2

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

57

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