T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
This table shows the preliminary power dissipation on the VDD_LP supply for the T2080
at allowable voltage levels.
Table 9. VDD_LP Power Dissipation
Supply
Maximum
Unit
Notes
VDD_LP (T2080 on, 65C)
1.5
mW
1
VDD_LP (T2080 off, 65C)
360
uW
2
VDD_LP (T2080 off, 40C)
132
uW
2
Notes:
1. VDD_LP = 1.0 V, TJ = 65 °C
2. When T2080 is off, VDD_LP may be supplied by battery power to retain the Zeroizable Master Key and other Trust
Architecture state. Board should implement a PMIC which switches VDD_LP to battery when SoC powered down. See T2080
Reference Manual Trust Architecture chapter for more information.
Table 10. T2080 Rev 1.1 single core/single cluster low-power mode power savings, 1.0 V
105°C1,2,3
Mode
Core
Frequency
= 1.8 GHz
Core
Frequency
= 1.533
GHz
Core
Frequency
= 1.2 GHz
Units
Comments
Notes
PH10
0.96
0.82
0.64
Watts
Savings realized moving from PH00 to PH10 1, 2, 4
state, single core
PH15
0.27
0.23
0.19
Watts
Savings realized moving from PH10 to PH15 1, 4, 5
state, single core
PH20
0.37
0.35
0.34
Watts
Savings realized moving from PH15 to PH20 1, 4
state, single core
PCL10 0.95
0.91
0.73
Watts
Savings realized moving from PH20 to PCL10 1
state, single cluster
LPM20 0.90
0.82
0.72
Watts Savings realized moving from PCL10 to
1
LPM20 state
LPM40 0.60
0.49
0.35
Watts Savings realized moving from LPM20 to
1
LPM40 state, single cluster
Notes:
1. Power for VDD only.
2. Typical power assumes Dhrystone running (PH00 state) with 70% activity factor.
3. Typical power based on nominal process distribution for this device.
4. PH10, PH15, PH20 power savings with one core. Maximum savings would be n times, where n is the number of used
cores.
5. Require both threads of the core to enter the same low-power mode.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
56
NXP Semiconductors
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