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T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 15. ECn_GTX_CLK125 DC electrical characteristics1
Parameter
Symbol
Min
Typical
Max
Unit
1. At recommended operating conditions with LVDD = 2.5 V.
2. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3.
3. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
Notes
This table provides the Ethernet gigabit reference clocks AC timing specifications.
Table 16. ECn_GTX_CLK125 AC timing specifications1
Parameter/Condition
Symbol
Min
Typical
Max
Unit Notes
ECn_GTX_CLK125 frequency
ECn_GTX_CLK125 cycle time
ECn_GTX_CLK125 rise and fall time
LVDD = 2.5 V
ECn_GTX_CLK125 duty cycle
1000Base-T for RGMII
tG125
tG125
tG125R/tG125F
125 - 100 ppm 125
8
tG125H/tG125
47
125 + 100 ppm MHz
ns
0.75
ns
2
53
%
3
ECn_GTX_CLK125 jitter
± 150
ps
3
Notes:
1. At recommended operating conditions with LVDD = 2.5 V ± 125 mV.
2. Rise and fall times for ECn_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V.
3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter with 2% degradation. The
ECn_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle
generated by the GTX_CLK. See RGMII AC timing specifications for duty cycle for 10Base-T and 100Base-T reference clock.
3.6.5 DDR clock timing
This section provides the DDR clock DC and AC timing specifications. DDR3L
maximum supported data rate is 1866 MT/s.
3.6.5.1 DDR clock DC timing specifications
This table provides the DDR clock (DDRCLK) DC specifications.
Table 17. DDRCLK DC electrical characteristics3
Parameter
Input high voltage
Input low voltage
Input capacitance
Symbol
VIH
VIL
CIN
Min
1.25
Typical
Max
0.6
12
Table continues on the next page...
Unit
V
V
pF
Notes
1
1
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
60
NXP Semiconductors

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