OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
OR2T15B7BA352-DB Datasheet PDF : 200 Pages
| |||
ORCA Series 2 FPGAs
Data Sheet
November 2006
Timing Characteristics (continued)
Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes) (continued)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Speed
-7
-8
Unit
Min
Max
Min
Max
Write Operation Setup Time:
S Address to Clock (A[3:0]/B[3:0] to CK)
MEMS_ASET
0.0
—
0.0
—
ns
Data to Clock (WD[3:0] to CK)
MEMS_DSET
0.0
—
0.0
—
ns
Write Enable (WREN) to Clock
MEMS_WRSET
0.0
—
0.0
—
ns
(A4 to CK)
E Write-port Enable (WPE) to Clock
MEMS_PWRSET
0.0
—
0.0
—
ns
(C0 to CK)
Write Operation Hold Time:
IC Address to Clock (A[3:0]/B[3:0] to CK)
MEMS_AHLD
1.0
—
0.8
—
ns
Data to Clock (WD[3:0] to CK)
MEMS_DHLD
1.0
—
0.8
—
ns
D Write Enable (WREN) to Clock
MEMS_WRHLD
1.0
—
0.8
—
ns
(A4 to CK)
Write-port Enable (WPE) to Clock
MEMS_PWRHLD
0.7
—
0.6
—
ns
V E (C0 to CK)
1. Readback of the configuration bit stream when simultaneously writing to a PFU in either SSPM fast mode or SDPM fast mode is not allowed.
2. Because the setup time of data into the latches/FFs is less than 0 ns, data written into the RAM can be loaded into a latch/FF in the same
E PFU on the next opposite clock edge (one-half clock period).
D INU A[3:0],B[3:0]
T WD[3:0]
C T A4 (WREN)
E N C0 (WPE)
L O CK
SE DISC F[3:0]
MEMS_ASET
MEMS_DSET
MEMS_WRSET
MEMS_PWRSET
TFSCH/TSCH
MEMS_AHLD
MEMS_DHLD
MEMS_WRHLD
MEMS_PWRHLD
TFSCL/TSCL
FMEMS_DEL/MEMS_DEL
Figure 60. Synchronous Memory Write Characteristics
5-4621(F).a
148
Lattice Semiconductor
Share Link: 