OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Timing Characteristics (continued)

Table 40A. OR2CxxA and OR2TxxA Synchronous Memory Read Characteristics (SSPM and SDPM Modes)

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Parameter

S Read Operation (TJ = 85 °C, VDD = min):

Read Cycle Time

Data Valid After Address

E (A[3:0], B[3:0] to F[3:0])

Read Operation, Clocking Data Into

Latch/FF (TJ = 85 °C, VDD = min):

IC Address to Clock Setup Time

(A[3:0], B[3:0] to CK)

D Clock to PFU Output—Register

(CK to Q[3:0])

Symbol

Speed

-3

-4

-5

-6

-7

Unit

Min Max Min Max Min Max Min Max Min Max

TRC

3.6 — 2.7 — 2.4 — 2.3 — 2.0 — ns

MEMS*_ADEL — 2.8 — 2.1 — 1.7 — 1.4 — 1.1 ns

MEMS*_ASET 1.8 — 1.2 — 1.1 — 1.0 — 0.9 — ns

REG_DEL — 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns

V E Table 40B. OR2TxxB Synchronous Memory Read Characteristics (SSPM and SDPM Modes)

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

E U +85°C.

Speed

D Parameter

Symbol

-7

-8

Unit

IN Min

Max

Min

Max

Read Operation (TJ = 85 °C, VDD = min):

Read Cycle Time

TRC

1.9

—

1.8

—

ns

T Data Valid After Address

MEMS*_ADEL

—

1.8

—

1.4

ns

T (A[3:0], B[3:0] to F[3:0])

Read Operation, Clocking Data into

Latch/FF (TJ = 85 °C, VDD = Min):

C N Address to Clock Setup Time

MEMS*_ASET

0.9

—

0.8

—

ns

(A[3:0], B[3:0] to CK)

Clock to PFU Output—Register

REG_DEL

—

1.0

—

1.0

ns

E (CK to Q[3:0])

L O A[3:0], B[3:0]

E C F[3:0]

S DIS CK

MEM*_ADEL

MEM*_ASET

REG_DEL

Q[3:0]

5-4622(F).r2.a

Figure 61. Synchronous Memory Read Cycle

Lattice Semiconductor

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