OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Timing Characteristics (continued)

Table 44A. OR2CxxA/OR2TxxA Global Clock to Output Delay (Pin-to-Pin)—Output Not on Same

Side of the Device as the Clock Pin

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C;

Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C; CL = 50 pF.

Description

S (TJ = 85 °C, VDD = min)

Device

Speed

-3

-4

-5

-6

-7

Unit

Min Max Min Max Min Max Min Max Min Max

CLK Input Pin → OUTPUT Pin OR2C/2T04A — 10.5 — 9.9 — 8.8 — — — — ns

E (Fast)

OR2C06A — 10.6 — 10.0 — 8.9 — — — — ns

OR2C/2T08A — 10.8 — 10.1 — 9.0 — — — — ns

OR2C/2T10A — 11.0 — 10.3 — 9.2 — — — — ns

IC OR2C12A — 11.2 — 10.5 — 9.4 — — — — ns

OR2C/2T15A — 11.5 — 10.7 — 9.6 — 8.9 — 7.3 ns

D OR2C/2T26A — 11.9 — 11.1 — 10.0 — 9.3 — 7.7 ns

OR2C/2T40A — 13.3 — 12.4 — 11.1 — 10.5 — 8.3 ns

CLK Input Pin → OUTPUT Pin OR2C/2T04A — 12.7 — 11.8 — 10.3 — — — — ns

V E (Slewlim)

OR2C06A — 12.9 — 11.9 — 10.4 — — — — ns

OR2C/2T08A — 13.1 — 12.0 — 10.5 — — — — ns

OR2C/2T10A — 13.3 — 12.2 — 10.6 — — — — ns

E OR2C12A — 13.5 — 12.4 — 10.8 — — — — ns

U OR2C/2T15A — 13.6 — 12.6 — 11.0 — 10.1 — 8.0 ns

OR2C/2T26A — 14.1 — 12.9 — 11.4 — 10.5 — 8.4 ns

OR2C/2T40A — 15.5 — 14.2 — 12.5 — 11.7 — 9.1 ns

D IN CLK Input Pin → OUTPUT Pin OR2C/2T04A — 14.8 — 13.8 — 13.4 — — — — ns

(Sinklim)

OR2C06A — 15.0 — 13.9 — 13.5 — — — — ns

OR2C/2T08A — 15.2 — 14.1 — 13.6 — — — — ns

OR2C/2T10A — 15.4 — 14.2 — 13.7 — — — — ns

T OR2C12A — 15.6 — 14.4 — 13.9 — — — — ns

T OR2C/2T15A — 15.8 — 14.6 — 14.1 — 12.7 — 11.2 ns

OR2C/2T26A — 16.2 — 14.9 — 14.4 — 13.1 — 11.6 ns

OR2C/2T40A — 17.6 — 16.3 — 15.6 — 14.3 — 12.2 ns

C N Notes:

The pin-to-pin timing information from ispLEVER is more accurate than this table. For earlier versions of ORCA Foundry, the pin-to-pin timing

parameters in this table should be used instead of results reported by ORCA Foundry.

E This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the

O PFU CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not

used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that the direct

L FF→I/O routing be used.

E C If the clock pin is not located at one of the four center PICs, this delay must be increased by up to the following amounts:

OR2C/2T04A = 1.5%, OR2C06A = 2.0%, OR2C/2T08A = 3.1%, OR2C/2T10A = 3.9%, OR2C12A = 4.9%, OR2C/2T15A = 5.7%,

S DIS OR2C/2T26A = 8.1%, OR2C/2T40A = 12.5%.

154

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