OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

November 2006

Timing Characteristics (continued)

Table 41A. OR2CxxA and OR2TxxA PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Speed

Parameter

Symbol

-3

-4

-5

-6

-7

Unit

Min Max Min Max Min Max Min Max Min Max

S PFU Output MUX (TJ = 85 °C, VDD = min)

Output MUX Delay (F[3:0]/Q[3:0] to O[4:0]) OMUX_DEL — 0.8 — 0.6 — 0.5 — 0.4 — 0.4 ns

PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)

E BIDI Propagation Delay

BIDI 3-state Enable/Disable Delay

TRI_DEL — 1.0 — 0.8 — 0.7 — 0.6 — 0.5 ns

TRIEN_DEL — 1.3 — 1.0 — 0.8 — 0.8 — 0.7 ns

Direct Routing (TJ = 85 °C, VDD = min)

IC PFU to PFU Delay (xSW)

D PFU Feedback (xSW)

DIR_DEL — 1.1 — 0.9 — 0.7 — 0.6 — 0.6 ns

FDBK_DEL — 0.8 — 0.7 — 0.6 — 0.5 — 0.5 ns

Table 41B. OR2TxxB PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics

V E OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

E U Speed

Parameter

Symbol

-7

-8

Unit

Min

Max

Min

Max

D IN PFU Output MUX (TJ = 85 °C, VDD = min)

Output MUX Delay (F[3:0]/Q[3:0] to O[4:0]) OMUX_DEL

—

0.4

—

0.4

ns

PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)

T BIDI Propagation Delay

T BIDI 3-state Enable/Disable Delay

TRI_DEL

—

0.7

—

0.6

ns

TRIEN_DEL

—

1.1

—

0.9

ns

Direct Routing (TJ = 85 °C, VDD = min)

PFU to PFU Delay (xSW)

SELDEICSCON PFU Feedback (xSW)

DIR_DEL

—

0.6

—

0.5

ns

FDBK_DEL

—

0.4

—

0.4

ns

150

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