OR2T15B7BA352-DB View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Timing Characteristics (continued)

Table 42A. OR2CxxA and OR2TxxA Internal Clock Delay

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Device

(TJ = 85 °C, VDD = min)

Symbol

-3

Speed

-4

-5

-6

-7

Unit

S Min Max Min Max Min Max Min Max Min Max

OR2C04A/OR2T04A CLK_DEL — 4.4 — 4.3 — 3.6 — — — —

ns

OR2C06A

CLK_DEL — 4.5 — 4.4 — 3.7 — — — —

ns

E OR2C08A/OR2T08A CLK_DEL — 4.6 — 4.5 — 3.8 — — — —

ns

OR2C10A/OR2T10A CLK_DEL — 4.7 — 4.6 — 3.9 — — — —

ns

IC OR2C12A

CLK_DEL — 4.8 — 4.7 — 4.0 — — — —

ns

OR2C15A/OR2T15A CLK_DEL — 4.9 — 4.8 — 4.1 — 3.9 — 3.3 ns

D OR2C26A/OR2T26A CLK_DEL — 5.1 — 5.0 — 4.2 — 4.0 — 3.4 ns

OR2C40A/OR2T40A CLK_DEL — 5.4 — 5.3 — 4.5 — 4.2 — 3.6 ns

V E Notes:

This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing

to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

E U Table 42B. OR2TxxB Internal Clock Delay

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

D +85 °C.

INSpeed

Device

(TJ = 85 °C, VDD = min)

Symbol

-7

-8

Unit

T Min

Max

Min

Max

T OR2T15B

CLK_DEL

—

3.6

—

3.1

ns

OR2T40B

CLK_DEL

—

3.8

—

3.3

ns

C Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock

SELDEISCON routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

Lattice Semiconductor

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