DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
10
0b
RO
Reserved (RSVD): Reserved.
9:0
0b
RO
Reserved (RSV1): Reserved.
Description
21.5.2.2
GPE0 Enable Register (GPE0EN)—Offset 4h
Access Method
Type: I/O Register
(Size: 32 bits)
GPE0EN: [GPE0BLK] + 4h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:18
0b
RO
Reserved (RSV2): Reserved.
17
0b
RW
PCIe Enable (PCIE): When set enables GPE0STS.PCIE to generate SCI/SMI.
16
0b
RW
Remote Management Unit Enable (RMU): When set enables GPE0STS.RMU to
generate SCI/SMI.
15
0b
RW
Device Enable (SCLT): When set enables GPE0STS.SCLT to generate SCI/SMI.
14
0b
RW
GPIO Enable (GPIO): When set enables GPE0STS.GPIO to generate SCI/SMI.
13
0b
RW
External GPE Enable (EGPE): When set enables GPE0STS.EGPE to generate SCI/SMI.
12
0b
RW
Thermal Enable (THRM): When set enables GPE0STS.THRM to generate SCI/SMI.
11
0b
RW
Software GPE Enable (SWGPE): When set enables GPE0STS.SWGPE to generate SCI/
SMI.
10
0b
RO
Reserved (RSVD): Reserved.
9:0
0b
RO
Reserved (RSV1): Reserved.
21.5.2.3
SMI Enable Register (SMIEN)—Offset 10h
Access Method
Intel® Quark SoC X1000
DS
822
October 2013
Document Number: 329676-001US
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