DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Type: I/O Register
(Size: 32 bits)
SMIEN: [GPE0BLK] + 10h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:18
0b
RO
Reserved (RSV2): Reserved.
17
0b
RW
PCIe Enable (PCIE): When set enables SMISTS.PCIE to generate SMI.
16
0b
RW
Remote Management Unit Enable (RMU): When set enables SMISTS.RMU to
generate SMI
15
0b
RW
Device Enable (SCLT): When set enables SMISTS.SCLT to generate SMI.
14:12
0b
RO
Reserved (RSV1): Reserved.
11
0b
RO
Reserved (RSVD): Reserved.
10
0b
RW
SERR Enable (SERR): When set enables SMISTS.SERR to generate SMI#
9
0b
RW
GPIO Enable (GPIO): When set enables SMISTS.GPIO to generate SMI#
8
0b
RW
External SMI Enable (ESMI): When set enables SMISTS.ESMI to generate SMI#
7
0b
RO
Reserved (RSVD): Reserved.
6
0b
RO
Reserved (RSVD): Reserved.
5
0b
RO
Reserved (RSVD): Reserved.
4
0b
RW
APM Enable (APM): When set enables SMISTS.APM to generate SMI#
3
0b
RW
SPI Enable (SPI): When set enables SMISTS.SPI to generate SMI#
2
0b
RW
Sleep (SLP): When set enables SMISTS.SLP to generate SMI#
1
0b
RW
Software Timer (SWT): When set enables SMISTS.SWT to generate SMI#
0
0b
RW
BIOS: When set enables SMISTS.BIOS to generate SMI#
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
823
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