DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
21.5.2.4
SMI Status Register (SMISTS)—Offset 14h
Access Method
Type: I/O Register
(Size: 32 bits)
SMISTS: [GPE0BLK] + 14h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31
30
29:18
17
16
15
14:12
11
10
9
8
7
6
5
4
3
2
0b
RW
0b
WO
0b
RO
0b
RW/1C
0b
RW/1C
0b
RW/1C
0b
RO
0b
RO
0b
RW/1C
0b
RW/1C
0b
RW/1C
0b
RO
0b
RO
0b
RO
0b
RW/1C
0b
RW/1C
0b
RW/1C
End of SMI (EOS): This bit is present only in the SMI Status register and not in SMI
Enable register. When set, the Legacy Bridge de-asserts SMI#. Cleared when the Legacy
Bridge asserts SMI#.
BIOS Release (BRLS): This bit is present only in the SMI Status register and not in
SMI Enable register. Causes SCI to be generated by the Legacy Bridge. Always reads 0.
Reserved (RSV2): Reserved.
PCIe Status (PCIE): Set when an Assert SMI message from PCIe Controller is
received.
Remote Management Unit Status (RMU): Set when an Assert SMI message from the
Remote Management Unit is received.
Device Status (SCLT): Set when the SMI# signal from Device:20 or Device:21 goes
active.
Reserved (RSV1): Reserved.
Reserved (RSVD): Reserved.
SERR Status (SERR): Set when DO_SERR message is received by the Legacy Bridge.
GPIO Status (GPIO): Set when a GPIO configured for SMI goes active.
External GPE Status (ESMI): Set when the SMI_B input signal goes active.
Reserved (RSVD): Reserved.
Reserved (RSVD): Reserved.
Reserved (RSVD): Reserved.
APM Status (APM): Set when a write to SWSMICTL is performed.
SPI Status (SPI): Set when SPI logic is requesting an SMI
Sleep (SLP): Set when a write occurs to PM1C.SLPEN
Intel® Quark SoC X1000
DS
824
October 2013
Document Number: 329676-001US
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