DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
31
30:4
3
2:0
0b
RW
0b
RO
0b
RW/O
0b
RW
Periodic SMI Enable (RES): When set, an SMIS.SWT will be set by the rate specified
by PSRS.
Reserved (RSV): Reserved.
SMI Lock (SMIL): When set, writes to SMIE have no effect. This bit is only cleared by
Core Well reset
Periodic SMI Rate Selection (PSRS): Indicates when the timer will time out and
cause an SMI#. All values are +/- 30us (RTC Clock). Valid values are:
000b - 1.5ms
001b - 16ms
010b - 32ms
011b - 64ms
100b - 8 sec
101b - 16 sec
110b - 32 sec
111b - 64 sec
21.5.2.7
Power Management Configuration Suspend Well Register (PMSW)—
Offset 2Ch
Access Method
Type: I/O Register
(Size: 32 bits)
PMSW: [GPE0BLK] + 2Ch
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
1
0b
RW
CPU BIST Enable (CBE): CPU BIST enable INIT functionality not supported.
0
0b
RW
DRAM Initialization Scratch pad (DRAMI): This bit does not affect hardware
functionality. It is provided as a BIOS scratchpad bit that is maintained through warm
resets.
21.5.2.8
Power Management Configuration RTC Well Register (PMRW)—Offset
30h
Access Method
Type: I/O Register
(Size: 32 bits)
PMRW: [GPE0BLK] + 30h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 0000000Bh
Intel® Quark SoC X1000
DS
826
October 2013
Document Number: 329676-001US
Share Link: 