DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Legacy Bridge—Intel® Quark SoC X1000
31
28
24
20
16
12
8
4
0
00000000000000000000000000001011
Bit
Default &
Range Access
Description
31:10
9
8:5
4
3
2
1
0
0b
RO
0b
RW/1C
0b
RO
0b
RW
1b
RW
0b
RW
1b
RW
1b
RW
Reserved (RSV2): Reserved.
Remote Management Unit Watchdog Trip Status (WDTS): This bit is set when the
Remote Management Unit watchdog timer expires, causing a system shutdown. It is
reset by warm and cold resets. It is maintained through the shutdown sequence that is
initiated via this trip
Reserved (RSV1): Reserved.
RTC Bias Resistor 4 (RTCB4): Adds 192K when de-asserted
RTC Bias Resistor 3 (RTCB3): Adds 96K when de-asserted
RTC Bias Resistor 2 (RTCB2): Adds 48K when de-asserted
RTC Bias Resistor 1 (RTCB1): Adds 24K when de-asserted
RTC Bias Resistor 0 (RTCB0): Adds 12K when de-asserted
21.5.3 ACPI PM1 Block
Table 116. Summary of I/O Registers—PM1BLK
Offset
Start
0h
2h
4h
8h
Offset End
Register ID—Description
1h
“PM1 Status Register (PM1S)—Offset 0h†on page 827
3h
“PM1 Enable Register (PM1E)—Offset 2h†on page 828
7h
“PM1 Control Register (PM1C)—Offset 4h†on page 829
Bh
“Power Management 1 Timer Register (PM1T)—Offset 8h†on page 830
Default
Value
0000h
0000h
00000000h
00000000h
21.5.3.1 PM1 Status Register (PM1S)—Offset 0h
Access Method
Type: I/O Register
(Size: 16 bits)
Default: 0000h
PM1S: [PM1BLK] + 0h
PM1BLK Type: PCI Configuration Register (Size: 32 bits)
PM1BLK Reference: [B:0, D:31, F:0] + 48h
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
827
Share Link: 