DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Legacy Bridge—Intel® Quark SoC X1000
Bit
Default &
Range Access
Description
1
0b
RW/1C
Software Timer (SWT): Set when the software SMI has expired.
0
0b
RW/1C
BIOS Status (BIOS): Set when software sets PM1C.GRLS.
21.5.2.5
General Purpose Event Control Register (GPEC)—Offset 18h
Access Method
Type: I/O Register
(Size: 32 bits)
GPEC: [GPE0BLK] + 18h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:2
0b
RO
Reserved (RSV): Reserved.
1
0b
WO
Software General Purpose Event (SWGPE): Sets GPE0S.SWGPE when written with
1. This bit always reads back as 0.
0
0b
RW
Thermal Polarity (TPOL): This bit controls the polarity of THRM_B needed to set
GPE0S.THRM. When set, a HIGH value on THRM_B will set GPE0S.THRM. When cleared,
a LOW value on THRM_B will set GPE0S.THRM.
21.5.2.6
Power Management Configuration Core Well Register (PMCW)—Offset
28h
Access Method
Type: I/O Register
(Size: 32 bits)
PMCW: [GPE0BLK] + 28h
GPE0BLK Type: PCI Configuration Register (Size: 32 bits)
GPE0BLK Reference: [B:0, D:31, F:0] + 4Ch
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
825
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