dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
GIE
DISI
SWTRAP
—
—
—
bit 15
U-0
—
bit 7
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
INT2EP
U-0
—
R/W-0
INT1EP
R/W-0
AIVTEN
bit 8
R/W-0
INT0EP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-9
bit 8
bit 7-3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1 = Interrupts and associated IECx bits are enabled
0 = Interrupts are disabled, but traps are still enabled
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
Unimplemented: Read as ‘0’
AIVTEN: Alternate Interrupt Vector Table is Enabled bit
1 = AIVT is enabled
0 = AIVT is disabled
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
2013-2016 Microchip Technology Inc.
DS70005144E-page 105