dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 7-6: INTCON4: INTERRUPT CONTROL REGISTER 4
U-0
—
bit 15
U-0
U-0
—
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 8
U-0
—
bit 7
U-0
U-0
—
—
U-0
U-0
U-0
R-0, HS, SC R-0, HS, SC
—
—
—
ECCDBE(1)
SGHT
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
SC = Software Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-2
bit 1
bit 0
Unimplemented: Read as ‘0’
ECCDBE: ECC Double-Bit Error Trap bit(1)
1 = ECC double-bit error trap has occurred
0 = ECC double-bit error trap has not occurred
SGHT: Software-Generated Hard Trap Status bit
1 = Software-generated hard trap has occurred
0 = Software-generated hard trap has not occurred
Note 1: ECC double-bit error causes a generic hard trap.
2013-2016 Microchip Technology Inc.
DS70005144E-page 107