T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
Table 121. Processor, platform, and memory clocking specifications (continued)
Characteristic
Maximum processor core frequency
Unit Notes
1200 MHz
1533 MHz
1800 MHz
Min
Max
Min
Max
Min
Max
FMan
see note 600
6
see note 700
6
see note 700
6
MHz 6
Notes:
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The core cluster can run at cluster group PLL/1, PLL/2, or PLL/4. For the PLL/1 case, the minimum frequency is 1000
MHz. With a minimum cluster group PLL frequency of 1000 MHz, this results in a minimum allowable core cluster frequency
of 250 MHz for PLL/4.
3. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/3L memory bus clock frequency is limited to min =
533 MHz.
4. The memory bus clock speed is dictated by its own PLL.
5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by half of the platform clock divided by the
IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.
6. The FMan minimum frequency is 132 MHz for SGMII (1.25G), 330 MHz for SGMII (2.5G), 359 MHz for XAUI, 391 MHz for
HiGig, 469 MHz for HiGig2, and 330 MHz for XFI.
7. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-
speed interfaces.
4.1.2.1 DDR clock ranges
The DDR memory controller can run only in asynchronous mode, where the memory bus
is clocked with the clock provided on the DDRCLK input pin, which has its own
dedicated PLL.
This table provides the clocking specifications for the memory bus.
Table 122. Memory bus clocking specifications
Characteristic
Min
Max
Unit
Notes
Memory bus clock frequency
Notes:
533
1066
MHz
1, 2, 3
1. Caution: The platform clock to SYSCLK ratio and core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:3] and Dn_MCK[0:3]_B output clocks, running at
half of the DDR data rate.
3. The memory bus clock speed is dictated by its own PLL.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
151
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