T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Hardware design considerations

For proper PCI Express operation, the platform clock frequency must be greater than or

equal to:

527 MHz x (PCI Express link width)

16

Figure 50. Gen 1 PEX minimum platform frequency

527 MHz x (PCI Express link width)

8

Figure 51. Gen 2 PEX minimum platform frequency

527 MHz x (PCI Express link width)

4

Figure 52. Gen 3 PEX minimum platform frequency

See section "Link Width," in the chip reference manual for PCI Express interface width

details. Note that "PCI Express link width" in the above equation refers to the negotiated

link width as the result of PCI Express link training, which may or may not be the same

as the link width POR selection. It refers to the widest port in use, not the combined

width of the number ports in use. For instance, if two x4 PCIe Gen3 ports are in use, 527

MHz platform frequency is needed to support by using Gen 3 equation (527 x 4 / 4, not

527 x 4 x 2 / 4).

For proper serial RapidIO operation, the platform clock frequency must be greater than or

equal to 525MHz.

4.2 Power supply design

4.2.1 Voltage ID (VID) controllable supply

To guarantee performance and power specifications, a specific method of selecting the

optimum voltage-level must be implemented when the chip is used. As part of the chip's

boot process, software must read the VID efuse values stored in the Fuse Status register

(FUSESR) and then configure the external voltage regulator based on this information.

This method requires a point of load voltage regulator for each chip. The VDD supply

should be separated from the Serdes 1.0V supply SnVDD. It is required in order to control

the VDD supply only.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

154

NXP Semiconductors

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