T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
SnVDD
Bulk and
decoupling
F1
capacitors
C1
C2
C3
F2
Linear regulator output
GND
Figure 55. SnVDD power supply filter circuit
Note the following:
• Please refer to Power-on ramp rate, for maximum SnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low noise dedicated switching regulator can also be
used. 10 mVp-p, 50kHz - 500MHz is the noise goal.
4.2.5 XnVDD power supply filtering
XnVDD may be supplied by a linear regulator or sourced by a filtered G1VDD. Systems
may design in both options to allow flexibility to address system noise dependencies.
However, for initial system bring-up, the linear regulator option is highly recommended.
An example solution for XnVDD filtering, where XnVDD is sourced from a linear
regulator, is illustrated in Figure 56. The component values in this example filter are
system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
XnVDD
Bulk and
decoupling
capacitors
F1
C1
C2
C3
F2
GND
Figure 56. XnVDD power supply filter circuit
Linear regulator output
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
161
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