T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
There is no standardized way to number the COP header; so emulator vendors have
issued many different pin numbering schemes. Some COP headers are numbered top-to-
bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others
number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the
numbering scheme, the signal placement recommended in Figure 59 is common to all
known emulators.
4.5.1.1 Termination of unused signals
If the JTAG interface and COP header will not be used, NXP recommends the following
connections:
• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is
asserted when the system reset signal (PORESET_B) is asserted, ensuring that the
JTAG scan chain is initialized during the power-on reset flow. NXP recommends
that the COP header be designed into the system as shown in Figure 60. If this is not
possible, the isolation resistor will allow future access to TRST_B in case a JTAG
interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.
COP_TDO
1
COP_TDI
3
NC
5
COP_TCK
7
COP_TMS
9
COP_SRESET_B
11
COP_HRESET_B
13
COP_CHKSTP_OUT_B
15
2
NC
4
COP_TRST_B
6
COP_VDD_SENSE
8
COP_CHKSTP_IN_B
10
NC
12
NC
KEY
No pin
16
GND
Figure 59. Legacy COP connector physical pinout
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
166
NXP Semiconductors
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