T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Where:
Hardware design considerations
• C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
• F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
USB_SVDD
Bulk and
decoupling
F1
VDD
capacitors
C1
C1
GND
Figure 58. USB_SVDD power supply filter circuit
4.3 Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can
generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other
components in the chip system, and the chip itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each VDD, OVDD, DVDD, G1VDD, and LVDD pin of the device.
These decoupling capacitors should receive their power from separate VDD, OVDD,
DVDD, G1VDD, LVDD, and GND power planes in the PCB, utilizing short traces to
minimize inductance. Capacitors may be placed directly under the device using a
standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount
technology) capacitors should be used to minimize lead inductance, preferably 0402 or
0603 sizes.
As presented in Core and platform supply voltage filtering, it is recommended that there
be several bulk storage capacitors distributed around the PCB, feeding the VDD and other
planes (for example, OVDD, DVDD, G1VDD, and LVDD), to enable quick recharging of
the smaller chip capacitors.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
163
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