T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
1 kΩ
OVDD
From target
board sources
(if any)
HRESET_B
PORESET_B
10 kΩ
7
HRESET_B6
10 kΩ
PORESET_B1
COP_HRESET_B
13
COP_SRESET_B
11
B
A
5
10 kΩ
10 kΩ
10 kΩ
1
2
3
4
10 kΩ
5
6
7
8
9
10
11
12
13
KEY
No pin
15
16
COP connector
physical pinout
COP_TRST_B
4
6 COP_VDD_SENSE2
5
NC
15 COP_CHKSTP_OUT_B
143
10 Ω
10 kΩ
8 COP_CHKSTP_IN_B
9 COP_TMS
1 COP_TDO
3 COP_TDI
7 COP_TCK
2
NC
10
NC
System logic
10 kΩ
TRST_B1
CKSTP_OUT_B
TMS
TDO
TDI
TCK
12
4
16
Notes:
1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
6. Asserting HRESET_B causes a hard reset on the device
7. This is an open-drain output gate.
Figure 60. Legacy JTAG interface connection
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
167
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