T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
• Operating range: 10 - 230 µA
• Ideality factor over 13.5 - 220 µA: Temperature range 25°C - 105°C n =
1.006833 ± 0.008
4.5.1 Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system
control pins as demonstrated in Figure 60. Care must be taken to ensure that these pins
are maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B
signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors
built on Power Architecture technology. The device requires TRST_B to be asserted
during power-on reset flow to ensure that the JTAG boundary logic does not interfere
with normal chip operation. While the TAP controller can be forced to the reset state
using only the TCK and TMS signals, generally systems assert TRST_B during the
power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the
JTAG interface is also used for accessing the common on-chip processor (COP), which
implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port
of the processor, with some additional status monitoring signals. The COP port requires
the ability to independently assert PORESET_B or TRST_B in order to fully control the
processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset
signals must be merged into these signals with logic.
The arrangement shown in Figure 60 allows the COP port to independently assert
PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.
The COP interface has a standard header, shown in Figure 59, for connection to the target
system, and is based on the 0.025" square-post, 0.100" centered header assembly (often
called a Berg header). The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and
memory examination/modification, and other standard debugger features. An inexpensive
option can be to leave the COP header unpopulated until needed.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
165
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