T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
Note the following:
• See Power-on ramp rate for maximum XnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft-start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10
mVp-p, 50 kHz - 500 MHz is the noise goal.
4.2.6 USB_HVDD and USB_OVDD power supply filtering
USB_HVDD and USB_OVDD must be sourced by a filtered 3.3 V and 1.8 V voltage
source using a star connection. An example solution for USB_HVDD and USB_OVDD
filtering, where USB_HVDD and USB_OVDD are sourced from a 3.3 V and 1.8 V voltage
source, is illustrated in the following figure. The component values in this example filter
is system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
USB_HVDD
or USB_OVDD
Bulk and
decoupling
capacitors
C1
C2
F1
C3
3.3 V or 1.8 V source
GND
Figure 57. USB_HVDD and USB_OVDD power supply filter circuit
4.2.7 USB_SVDD power supply filtering
USB_SVDD must be sourced by a filtered VDD using a star connection. An example
solution for USB_SVDD filtering, where USB_SVDD is sourced from VDD, is illustrated
in the following figure. The component values in this example filter is system dependent
and are still under characterization, component values may need adjustment based on the
system or environment noise.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
162
NXP Semiconductors
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