T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
AVDD_Dn voltages must be derived directly from a 1.8 V voltage source through a low
frequency filter scheme. AVDD_ SDn_PLLn voltages must be derived directly from the
XnVDD source through a low frequency filter scheme. The recommended solution for
PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated
in Figure 53, one for each of the AVDD pins. By providing independent filters to each
PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This
circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to
10 MHz range.
Each circuit should be placed as close as possible to the specific AVDD pin being
supplied to minimize noise coupled from nearby circuits. It should be possible to route
directly from the capacitors to the AVDD pin, which is on the periphery of the footprint,
without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Where:
• R = 5 Ω ± 5%
• C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
• C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH
NOTE
A higher capacitance value for C2 may be used to improve
the filter as long as the other C2 parameters do not change
(0402 body, X5R, ESL ≤ 0.5 nH).
NOTE
Voltage for AVDD is defined at the input of the PLL supply
filter and not the pin of AVDD.
1.8 V source
R
C1
AVDD_PLAT, AVDD_CGAn, AVDD_D1
C2
Low-ESL surface-mount capacitors
GND
Figure 53. PLL power supply filter circuit
The AVDD_ SDn_PLLn signals provides power for the analog portions of the SerDes
PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered
using a circuit similar to the one shown in following Figure 54. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_ SDn_PLLn
balls to ensure it filters out as much noise as possible. The ground connection should be
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
159
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