T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
near the AVDD_ SDn_PLLn balls. The 0.003-µF capacitors closest to the balls, followed
by a 4.7-µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane.
The capacitors are connected from AVDD_ SDn_PLLn to the ground plane. Use ceramic
chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
XnVDD
0.33 Ω
47 µF
4.7 µF
0.003 µF
AVDD_SDn_PLLn
AGND_SDn_PLLn
Figure 54. SerDes PLL power supply filter circuit
Note the following:
• AVDD_ SDn_PLLn should be a filtered version of XnVDD.
• Signals on the SerDes interface are fed from the XnVDD power plane.
• Voltage for AVDD_ SDn_PLLn is defined at the PLL supply filter and not the pin of
AVDD_ SDn_PLLn.
• A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are
recommended. The size and material type are important. A 0.33-Ω ± 1% resistor is
recommended.
• There needs to be dedicated analog ground, AGND_ SDn_PLLn for each AVDD_
SDn_PLLn pin up to the physical local of the filters themselves.
4.2.4 SnVDD power supply filtering
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for SnVDD filtering, where SnVDD is sourced from a linear
regulator, is illustrated in Figure 55. The component values in this example filter are
system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
160
NXP Semiconductors
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