Hardware design considerations
4.1.3 SerDes PLL ratio
The clock ratio between each of the two SerDes PLLs and their respective externally
supplied SDn_REF_CLKn_P/SDn_REF_CLKn_N inputs is determined by a set of RCW
Configuration fields-SRDS_PRTCL_Sn, SRDS_PLL_REF_CLK_SEL_Sn, and
SRDS_DIV_*_Sn-as shown in this table.
Table 123. Valid SerDes RCW encodings and reference clocks
SerDes protocol (given
lane)
Valid reference
clock
frequency
Legal setting for
SRDS_PRTCL_Sn
Legal setting
for
SRDS_PLL_RE
F_CLK_SEL_Sn
Legal setting for
SRDS_DIV_*_Sn
Notes
High-speed serial and debug interfaces
PCI Express 2.5 GT/s
100 MHz
Any PCIe
0b0: 100 MHz 2b10: 2.5 G
1
(doesn't negotiate upwards) 125 MHz
0b1: 125 MHz
1
PCI Express 5 GT/s
100 MHz
Any PCIe
0b0: 100 MHz 2b01: 5.0 G
1
(can negotiate up to 5 GT/s) 125 MHz
0b1: 125 MHz
1
PCI Express 8 GT/s
100 MHz
Any PCIe
0b0: 100 MHz 2b00: 8.0 G
1
(can negotiate up to 8 GT/s) 125 MHz
0b1: 125 MHz
1
Serial RapidIO 2.5 GBaud
100 MHz
SRIO @ 2.5/5 GBaud
0b0: 100 MHz 0b1: 2.5 G
-
125 MHz
0b1: 125 MHz
-
Serial RapidIO 3.125 GBaud 125 MHz
SRIO @ 3.125 GBaud 0b0: 125 MHz Don't care
-
156.25 MHz
0b1: 156.25 MHz
-
Serial RapidIO 5 GBaud
100 MHz
SRIO @ 2.5/5 GBaud
0b0: 100 MHz 0b0: 5.0 G
-
125 MHz
0b1: 125 MHz
-
SATA (1.5 or 3 Gbps)
100 MHz
Any SATA
0b0: 100 MHz Don't care
2
125 MHz
0b1: 125 MHz
Debug (2.5 GBaud)
100 MHz
Aurora @ 2.5/5 GBaud 0b0: 100 MHz 0b1: 2.5 G
-
125 MHz
0b1: 125 MHz
-
Debug (5 GBaud)
100 MHz
Aurora @ 2.5/5 GBaud 0b0: 100 MHz 0b0: 5.0 G
-
125 MHz
0b1: 125 MHz
-
Networking interfaces
SGMII (1.25 GBaud)
100 MHz
SGMII @ 1.25 GBaud
0b0: 100 MHz Don't care
-
125 MHz
1000Base-KX @ 1.25
0b1: 125 MHz
-
GBaud
2.5x SGMII (3.125 GBaud) 125 MHz
SGMII @ 3.125 GBaud 0b0: 125 MHz Don't care
-
156.25 MHz
0b1: 156.25 MHz
-
XAUI (3.125 GBaud)
125 MHz
XAUI @ 3.125 GBaud
0b0: 125 MHz Don't care
-
156.25 MHz
0b1: 156.25 MHz
-
HiGig or HiGig2 (3.125
125 MHz
HiGig @ 3.125 GBaud 0b0: 125 MHz Don't care
-
GBaud)
156.25 MHz
0b1: 156.25 MHz
-
HiGig or HiGig2 (3.75 GBaud) 125 MHz
HiGig @ 3.75 GBaud
0b0: 125 MHz Don't care
-
156.25 MHz
0b1: 156.25 MHz
-
Table continues on the next page...
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
152
NXP Semiconductors