T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
2. As part of the chip's boot process, software must read the efuse values stored in the
FUSESR and then configure the voltage regulator based on this information. The
software decides on a new configuration and sends this value across the IFC, eSPI, or
any other interface that is used to connect to the FPGA/ASIC or separate power-
management device that manages the regulator. Note that some regulators may
require a series of writes so that the voltage is slowly stepped from its old to its new
value.
3. When the voltage has stabilized, software adjusts the operating frequencies as
desired.
Upon completion of configuration, some regulators may have a write-protect pin to
prevent undesired data changes after configuration is complete. A single GPIO pin on the
chip could be allocated for this task, if desired.
4.2.2 Core and platform supply voltage filtering
The VDD supply is normally derived from a high current capacity linear or switching
power supply which can regulate its output voltage very accurately despite changes in
current demand from the chip within the regulator's relatively low bandwidth. Several
bulk decoupling capacitors must be distributed around the PCB to supply transient
current demand above the bandwidth of the voltage regulator.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to
ensure the quick response time necessary. They should also be connected to the power
and ground planes through two vias to minimize inductance. However, customers should
work directly with their power regulator vendor for best values and types of bulk
capacitors.
As a guideline for customers and their power regulator vendors, NXP recommends that
these bulk capacitors should be chosen to maintain the positive transient power surges to
less than VID + 50 mV (negative transient undershoot should comply with specification
of VID - 30mV) for current steps of up to 10 A with a slew rate of 12 A/us.
These bulk decoupling capacitors will ideally supply a stable voltage for current
transients into the megahertz range. Above that, see Decoupling recommendations for
further decoupling recommendations.
4.2.3 PLL power supply filtering
Each of the PLLs described in System clocking is provided with power through
independent power supply pins (AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
AVDD_Dn and AVDD_ SDn_PLLn). AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
158
NXP Semiconductors
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