T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
NOTE
During the power-on reset process, the fuse values are read and
stored in the FUSESR. It is expected that the chip's boot code
reads the FUSESR value very early in the boot sequence and
updates the regulator accordingly.
The default voltage regulator setting that is safe for the system to boot is the
recommended operating VDD at initial start-up of 1.025V. It is highly recommended to
select a regulator with a Vout range of at least 0.9V to 1.1V, with a resolution of 12.5mV
or better, when implementing a VID solution.
The table below lists the valid VID efuse values that will be programmed at the factory
for this chip.
Table 125. Fuse Status Register
(DCFG_CCSR_FUSESR)
Binary value of DA_V / DA_ALT_V
00000
00001
00010
10000
10001
10010
VDD voltage
1.0250 V
0.9875 V
0.9750 V
1.0000 V
1.0125 V
1.0250 V
For additional information on VID, please refer to the chip reference manual.
4.2.1.1 Options for system design
There are several widely-accepted options available to the system designer for obtaining
the benefits of a VID solution. The most common option is to use the VID solution to
drive a system's controllable voltage-regulators through a sideband interface such as a
simple parallel bus or PMBus interface. PMbus is similar to I2C but with extensions to
improve robustness and address shortcomings of I2C; the PMBus specification can be
found at www.pmbus.org. The simple parallel bus is supported by the chip through GPIO
pins and the PMBus interface is supported by an I2C interface. Other VID solutions may
be to access an FPGA/ASIC or separate power management chip through the IFC, SPI, or
other chip-specific interface, where the other device then manages the voltage regulator.
The method chosen for implementing the chip-specific voltage in the system is decided
by the user.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
155
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