T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Hardware design considerations
Table 123. Valid SerDes RCW encodings and reference clocks (continued)
SerDes protocol (given
lane)
Valid reference
clock
frequency
Legal setting for
SRDS_PRTCL_Sn
Legal setting
for
SRDS_PLL_RE
F_CLK_SEL_Sn
Legal setting for
SRDS_DIV_*_Sn
Notes
XFI (10.3125 GBaud)
156.25 MHz
XFI @ 10.3125 GBaud 0b0: 156.25 MHz Don't care
-
10GBase-KR (10.3125GBaud) 156.25 MHz
10GBase-KR @ 10.3125 0b0: 156.25 MHz Don't care
-
GBaud
Notes:
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such as
sRIO, SATA, or debug is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.
2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the
SATA IP itself. It is possible for software to set each SATA at different rates.
4.1.4 Frequency options
This section discusses interface frequency options.
4.1.4.1 SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
Table 124. SYSCLK and platform frequency options
Platform: SYSCLK ratio
SYSCLK (MHz)
66.67
100.00
133.33
Platform frequency (MHz)1
3:1
400
4:1
400
533
5:1
500
6:1
400
600
7:1
466
8:1
533
9:1
600
Notes:
1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed).
4.1.4.2 Minimum platform frequency requirements for high-speed
interfaces
The platform clock frequency must be considered for proper operation of high-speed
interfaces as described below.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
153
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