STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

VI - MEMORY TIMING

VI.1 - Dynamic Memories

Figure 31 : Dynamic Memory Read Signals from the Multi-HDLC

NDS fro m µP

T

(or e quivalent)

a

MAS TE RC LO CK

a pplied to XTAL1 P in

Total Re ad Cycle

a

a

a

1/f

a

a

NRAS 0/3

HZ

Tu

HZ

NCAS 0/1

NWE

ADM0/10

Tv

Tv/2

Tw

Tz

NOE

Tw + Tz /2

DM0/15 from

DRAM Circuit

Ts

Th

HZ

HZ

Note : S e e

E ach s ignal from the MHDLC is high

MBL De finition

impe dance outside this time if MBL = 0

Symbol

T

a

Tw

Tz

Ts

Th

Parameter

Delay between Data Strobe from the mP and beginning of cycle

Delay between Masterclock and Edge of each signal delivered by the

MHDLC (30pF)

Delay between NCAS Falling Edge and NCAS rising Edge

Delay between NCAS Rising Edge and end of cycle

Set-up Time Data /NCAS Rising Edge

Hold Time Data/NCAS Rising Edge

Min.

2/f

1/f

1/f

20

0

Typ.

20

Max.

2/f

2/f

Unit

ns

ns

ns

ns

ns

42/83

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