STLC5464 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5464 Datasheet PDF : 83 Pages
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STLC5464
VI - MEMORY TIMING (continued)
Figure 32 : Dynamic Memory Write Signals from the Multi-HDLC
NDS fro m µP
T
(or equivalent)
a
MASTE RCLOCK
a pplied to XTAL1 P in
Tota l Write Cycle
a
a
a
1/f
a
a
NRAS 0/3
HZ
Tu
HZ
NCAS 0/1
Tv
Tw
Tz
NWE
Tv/2
ADM0/10
Td
DM0/15
NOE
HZ
HZ
No te : S e e
Ea ch s ignal from the MHDLC is high
MBL Definition
impe dance outside this time if MBL = 0
Symbol
1/f
Tu
Tv
Tw
Tz
Tv/2
Td
Parameter
f : Masterclock Frequency
Delay between beginning of cycle and NRAS Falling Edge
Delay between NRAS Falling Edge and NCAS Falling Edge
Delay between NCAS Falling Edge and NWE Rising Edge
Delay between NWE Rising Edge and end of cycle
Delay between NRAS Falling Edge and address change
Data Valid after beginning of cycle (30 pF)
Note : Total Cycle : Tu + Tv + Tw + Tz
Min.
32
1/f
1/f
1/f
1/f
1/2f
1/f
Typ.
Max.
33
2/f
2/f
2/f
2/f
1/f
1/f
Unit
MHz
ns
ns
ns
ns
ns
ns
43/83
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